> For the complete documentation index, see [llms.txt](https://developer-mina.gitbook.io/setify/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://developer-mina.gitbook.io/setify/datasets/computer-science.md).

# Computer Science

### `logic_gate_not()`

A **NOT gate** (also often called **Inverter**) is a logic gate.

{% tabs %}
{% tab title="Data" %}

```
   x  y
0  0  1
1  1  0
```

{% endtab %}

{% tab title="Information" %}

```
RangeIndex: 2 entries, 0 to 1
Data columns (total 2 columns):
 #   Column  Non-Null Count  Dtype
---  ------  --------------  -----
 0   x       2 non-null      int64
 1   y       2 non-null      int64
dtypes: int64(2)
memory usage: 160.0 bytes
None
```

{% endtab %}
{% endtabs %}

### `logic_gate_and()`

The **AND gate** is a basic digital logic gate that implements a logical conjunction.

{% tabs %}
{% tab title="Data" %}

```
   x1  x2  y
0   0   0  0
1   0   1  0
2   1   0  0
3   1   1  1
```

{% endtab %}

{% tab title="Information" %}

```
RangeIndex: 4 entries, 0 to 3
Data columns (total 3 columns):
 #   Column  Non-Null Count  Dtype
---  ------  --------------  -----
 0   x1      4 non-null      int64
 1   x2      4 non-null      int64
 2   y       4 non-null      int64
dtypes: int64(3)
memory usage: 224.0 bytes
None
```

{% endtab %}
{% endtabs %}

### `�logic_gate_or()`

The **OR gate** is a digital logic gate that implements logical disjunction.

{% tabs %}
{% tab title="Data" %}

```
   x1  x2  y
0   0   0  0
1   0   1  1
2   1   0  1
3   1   1  1

```

{% endtab %}

{% tab title="" %}

```
RangeIndex: 4 entries, 0 to 3
Data columns (total 3 columns):
 #   Column  Non-Null Count  Dtype
---  ------  --------------  -----
 0   x1      4 non-null      int64
 1   x2      4 non-null      int64
 2   y       4 non-null      int64
dtypes: int64(3)
memory usage: 224.0 bytes
None
```

{% endtab %}
{% endtabs %}

### `logic_gate_nand()`

In digital electronics, a **NAND gate** (**NOT-AND**) is a logic gate which produces an output which is false only if all its inputs are true.

{% tabs %}
{% tab title="Data" %}

```
   x1  x2  y
0   0   0  1
1   0   1  1
2   1   0  1
3   1   1  0
```

{% endtab %}

{% tab title="Information" %}

```
RangeIndex: 4 entries, 0 to 3
Data columns (total 3 columns):
 #   Column  Non-Null Count  Dtype
---  ------  --------------  -----
 0   x1      4 non-null      int64
 1   x2      4 non-null      int64
 2   y       4 non-null      int64
dtypes: int64(3)
memory usage: 224.0 bytes
None
```

{% endtab %}
{% endtabs %}

### `logic_gate_nor()`

The **NOR gate** is a digital logic gate that implements logical NOR - it behaves according to the truth table below.

{% tabs %}
{% tab title="Data" %}

```
   x1  x2  y
0   0   0  1
1   0   1  0
2   1   0  0
3   1   1  0
```

{% endtab %}

{% tab title="Information" %}

```
RangeIndex: 4 entries, 0 to 3
Data columns (total 3 columns):
 #   Column  Non-Null Count  Dtype
---  ------  --------------  -----
 0   x1      4 non-null      int64
 1   x2      4 non-null      int64
 2   y       4 non-null      int64
dtypes: int64(3)
memory usage: 224.0 bytes
None
```

{% endtab %}
{% endtabs %}

### `logic_gate_xor()`

**XOR gate** (sometimes **EOR**, or **EXOR** and pronounced as **Exclusive OR**) is a digital logic gate that gives a true (1 or HIGH) output when the number of true inputs is odd.

{% tabs %}
{% tab title="Data" %}

```
   x1  x2  y
0   0   0  0
1   0   1  1
2   1   0  1
3   1   1  0
```

{% endtab %}

{% tab title="Information" %}

```
Int64Index: 4 entries, 0 to 3
Data columns (total 3 columns):
 #   Column  Non-Null Count  Dtype
---  ------  --------------  -----
 0   x1      4 non-null      int64
 1   x2      4 non-null      int64
 2   y       4 non-null      int64
dtypes: int64(3)
memory usage: 128.0 bytes
None
```

{% endtab %}
{% endtabs %}

### `logic_gate_xnor()`

The **XNOR gate** (sometimes **XORN'T**, **ENOR**, **EXNOR,** or **NXOR** and pronounced as **Exclusive NOR**) is a digital logic gate whose function is the logical complement of the exclusive OR (XOR) gate.

{% tabs %}
{% tab title="Data" %}

```
   x1  x2  y
0   0   0  1
1   0   1  0
2   1   0  0
3   1   1  1
```

{% endtab %}

{% tab title="Information" %}

```
RangeIndex: 4 entries, 0 to 3
Data columns (total 3 columns):
 #   Column  Non-Null Count  Dtype
---  ------  --------------  -----
 0   x1      4 non-null      int64
 1   x2      4 non-null      int64
 2   y       4 non-null      int64
dtypes: int64(3)
memory usage: 224.0 bytes
None
```

{% endtab %}
{% endtabs %}